compiler.config ≡
Compiler configuration parameters.
The Compiler uses constants defined in this module as configuration parameters for code generation.
Values of the parameters are imported from compiler.config.device, which combines default parameter values with device-specific values defined in in a device-specific module hardware.device.
Your device, either directly or indirectly, MUST define values for each of these constants.
const auto version = version §
Version of device configuration schema
const string device_name = device_name §
Unambiguous name of the target device
const string vendor = vendor §
Name of the vendor that manufactures the target device, for example ‘Intel’ or ‘Xilinx’
const string device_family = device_family §
Name of the device family into which the target device belongs, for example ‘Agilex 7’
const string hal_device_family = hal_device_family §
Name of the device family that is significant to the Vendor RTL (or simulation libraries). This value is passed into HAL modules as a parameter, and in some cases passed down into the Vendor modules or used to enable or disable some conditional behavior.
const bool trade_area_for_speed = trade_area_for_speed §
const bool supports_dsp = (integer_mul_src_width != 0) §
const auto integer_mul_src_width = integer_mul_src_width §
Width of source operands for an unsigned integer multiplication using a device DSP
const string unsigned_integer_mul_name = unsigned_integer_mul_name §
Name of the intrinsic operation for 1 unsigned integer multiplication using a device DSP
const string signed_integer_mul_name = signed_integer_mul_name §
Name of the intrinsic operation for 1 signed integer multiplication using a device DSP
const auto min_fifo_depth = min_fifo_depth §
Minimum depth for a single clock fifo
const auto min_dual_clock_fifo_depth = min_dual_clock_fifo_depth §
Minimum depth for a dual clock fifo
const auto min_almost_full_depth = min_almost_full_depth §
Minimum almost_full value for a fifo. This is the minimum value needed to overcome fifo read->almost_full latency
const auto almost_empty_depth = almost_empty_depth §
Minimum value for the almost empty threshold for a single-clock FIFO
const auto fifo_width_alignment = fifo_width_alignment §
Minimum width of LUTram based FIFO structures below which there are no area savings. Used in calculations for the local data propagation optimization
const auto fifo_depth_alignment = fifo_depth_alignment §
Minimum depth of LUTram based FIFO structures below which there are no area savings. Used in calculations for the local data propagation optimization
const auto fifo_fixed_cost = fifo_fixed_cost §
Fixed cost of a FIFO used in calculations for the local data propagation optimization Used in calculations for the local data propagation optimization
const auto fifo_bits_per_register = fifo_bits_per_register §
The number of bits in an implicit fifo that has the same area cost as 1 pipeline register. Used in calculations for the local data propagation optimization
const bool use_internal_buffer_fifo_optimization = use_internal_buffer_fifo_optimization §
true if it makes sense to use KanagawaInternalBufferFifo
for basic blockswith start conditions as an Fmax optimization
const bool fifo_depth_pow2 = fifo_depth_pow2 §
true if FIFO depths should be round up to a power of
2
const bool use_thread_rate_in_fifo_sizing = use_thread_rate_in_fifo_sizing §
true if basic block thread rates should be used when computing fifo depths. When set to false, a thread rate of 1 is assumed for sizing. This feature is used to work around an EDA tool bug for certain Intel devices.
const bool supports_auto_pipelining = supports_auto_pipelining §
true if the platform supports a feature where the EDA tool chooses the number of additional pipeline registers to add as needed to improve placement and routing
const auto min_auto_pipeline_depth = min_auto_pipeline_depth §
On platforms that support auto-pipelining, there is a mininum fixed depth of pipeline registers required.
const string verilog_dont_merge_pragma_name = verilog_dont_merge_pragma_name §
The Verilog pragma used to tell the synthesis tool not to merge a register with others
const bool supports_luts = supports_luts §
true if the device supports LUTs (should be true for all FPGAs)
const auto small_lut_size = small_lut_size §
//| Multiple LUTs of this size can fit into 1 resource (ALM, CLB)
const bool lut_based_shift_register_available = lut_based_shift_register_available §
true if the platform supports a RAM-based shift register. Used in calculations for the local data propagation optimization
const bool registers_require_power_on_initial_value = registers_require_power_on_initial_value §
true if control signals should have power-on value specified
const bool block_ram_supports_hardened_bypass = block_ram_supports_hardened_bypass §
If the block RAMs in the device support pipeline bypass (aka memory forwarding) for at least 2 stages
const bool block_ram_supports_ecc = block_ram_supports_ecc §
true if the device supports ECC for block RAMs
const bool block_ram_supports_true_dual_port = block_ram_supports_true_dual_port §
true if the device supports block RAMs in a true dual-port configuration (i.e. two independent read/write ports).
const bool block_ram_supports_quad_port = block_ram_supports_quad_port §
true if the device supports block RAMs in a simple quad-port configuration
const auto global_data_propagation_ram_alignment = global_data_propagation_ram_alignment §
For data propagation memories, the minimum width of 1 memory
const MemoryInitFileType memory_init_file_type = memory_init_file_type §
The format to use for memory initialization files
const auto memory_configurations = memory_configurations §
Valid memory configurations
const auto memory_resources = memory_resources §
Specifies the number of each type of memory resource that is available on the device.
const float32 array_mux_cost_factor = array_mux_cost_factor §
This value is multiplied by the number of muxes necessary to implement an array when estimating. the relative cost of synthesizing a memory structure as an array (logic) versus using a RAM primitive.
const float32 array_register_cost_factor = array_register_cost_factor §
This value is multiplied by the number of registers necessary to implement an array when estimating. the relative cost of synthesizing a memory structure as an array (logic) versus using a RAM primitive.
const float32 array_write_port_cost_factor = array_write_port_cost_factor §
This value is multiplied by the number of write ports necessary to implement an array when estimating. the relative cost of synthesizing a memory structure as an array (logic) versus using a RAM primitive.
const auto default_clock_frequency_mhz = 200 §