processor.risc_v.isa ≡

RISC-V ISA types, constants and helper functions.

enum Base : uint2 §source

Base ISA identifier

Values

```
RV32I §source
```
```
RV32E §source
```
```
RV64I §source
```

enum Extension : uint1 §source

Standard ISA extension identifier

Values

```
None = 0 §source
```
```
M = 1 §source
```

using Funct7 = uint7 §source

template <Base ISA>
class Types §source

Data types for specified base ISA

Aliases

using int_t = int<Types::int_size> §source

Signed XLEN bits wide integer

using uint_t = uint<Types::int_size> §source

Unsigned XLEN bits wide integer

using register_index_t = index_t<Types::registers> §source

Types

struct Decoded §source

Decoded instruction fields

Fields

optional<Types::register_index_t> rd §source

Destination register

optional<Types::register_index_t> rs1 §source

First operand register

optional<Types::register_index_t> rs2 §source

Second operand register

```
Types::int_t imm §source
```
Immediate operand (not valid for R-type instructions)
```
Funct7 funct7 §source
```
funct7 field (valid only for R-type instructions)

enum RVG : uint5 §source

General-purpose ISA major opcodes

Values

```
LOAD §source
```
```
LOAD_FP §source
```
```
custom_0 §source
```
```
MISC_MEM §source
```
```
OP_IMM §source
```
```
AUIPC §source
```
```
OP_IMM_32 §source
```
```
long0 §source
```
```
STORE §source
```
```
STORE_FP §source
```
```
custom_1 §source
```
```
AMO §source
```
```
OP §source
```
```
LUI §source
```
```
OP_32 §source
```
```
long1 §source
```
```
MADD §source
```
```
MSUB §source
```
```
NMSUB §source
```
```
NMADD §source
```
```
OP_FP §source
```
```
reserved0 §source
```
```
custom_2 §source
```
```
long2 §source
```
```
BRANCH §source
```
```
JALR §source
```
```
reserved1 §source
```
```
JAL §source
```
```
SYSTEM §source
```
```
reserved2 §source
```
```
custom_3 §source
```
```
long3 §source
```

using Funct3 = uint3 §source

enum Op : Funct3 §source

OP/OP_IMM minor opcodes

Values

```
ADD = 0 §source
```
```
SLL = 1 §source
```
```
SLT = 2 §source
```
```
SLTU = 3 §source
```
```
XOR = 4 §source
```
```
SR = 5 §source
```
```
OR = 6 §source
```
```
AND = 7 §source
```

enum MulDiv : Funct3 §source

“M” standard extension minor opcodes

Values

```
MUL = 0 §source
```
```
MULH = 1 §source
```
```
MULHSU = 2 §source
```
```
MULHU = 3 §source
```
```
DIV = 4 §source
```
```
DIVU = 5 §source
```
```
REM = 6 §source
```
```
REMU = 7 §source
```

enum Branch : Funct3 §source

BRANCH minor opcodes

Values

```
BEQ = 0 §source
```
```
BNE = 1 §source
```
```
BLT = 4 §source
```
```
BGE = 5 §source
```
```
BLTU = 6 §source
```
```
BGEU = 7 §source
```

enum LoadStore : Funct3 §source

LOAD/STORE minor opcodes

Values

```
B = 0 §source
```
```
H = 1 §source
```
```
W = 2 §source
```
```
BU = 4 §source
```
```
HU = 5 §source
```

enum System : Funct3 §source

SYSTEM minor opcodes

Values

```
PRIV = 0 §source
```
```
CSRRW = 1 §source
```
```
CSRRS = 2 §source
```
```
CSRRC = 3 §source
```
```
CSRRWI = 5 §source
```
```
CSRRSI = 6 §source
```
```
CSRRCI = 7 §source
```

enum MiscMem : Funct3 §source

MISC_MEM mino opcodes

Values

```
FENCE = 0 §source
```

using Reg = uint5 §source

enum ABI : Reg §source

Mnemonics for integer registers in the standard calling convention

Values

```
zero = 0 §source
```
Hard-wired zero
```
ra = 1 §source
```
Return address
```
sp = 2 §source
```
Stack pointer
```
gp = 3 §source
```
Global pointer
```
tp = 4 §source
```
Thread pointer
```
t0 = 5 §source
```
Temporary/alternate link register
```
t1 = 6 §source
```
Temporary
```
t2 = 7 §source
```
Temporary
```
s0 = 8 §source
```
Frame pointer
```
s1 = 9 §source
```
Saved register
```
a0 = 10 §source
```
Function arguments/return values
```
a1 = 11 §source
```
Function arguments/return values
```
a2 = 12 §source
```
Function arguments
```
a3 = 13 §source
```
Function arguments
```
a4 = 14 §source
```
Function arguments
```
a5 = 15 §source
```
Function arguments
```
a6 = 16 §source
```
Function arguments
```
a7 = 17 §source
```
Function arguments
```
s2 = 18 §source
```
Saved register
```
s3 = 19 §source
```
Saved register
```
s4 = 20 §source
```
Saved register
```
s5 = 21 §source
```
Saved register
```
s6 = 22 §source
```
Saved register
```
s7 = 23 §source
```
Saved register
```
s8 = 24 §source
```
Saved register
```
s9 = 25 §source
```
Saved register
```
s10 = 26 §source
```
Saved register
```
s11 = 27 §source
```
Saved register
```
t3 = 28 §source
```
Temporary
```
t4 = 29 §source
```
Temporary
```
t5 = 30 §source
```
Temporary
```
t6 = 31 §source
```
Temporary

template <auto N>
inline int32 sign_extend(uint<N> x) §source

Sign-extend an integer to XLEN bits

struct R_type §source

R-type instruction format

Fields

```
Opcode opcode §source
```
```
Reg rd §source
```
```
Funct3 funct3 §source
```
```
Reg rs1 §source
```
```
Reg rs2 §source
```
```
Funct7 funct7 §source
```

struct I_type §source

I-type instruction format

Fields

```
Opcode opcode §source
```
```
Reg rd §source
```
```
Funct3 funct3 §source
```
```
Reg rs1 §source
```
```
uint12 imm_11_0 §source
```

struct S_type §source

S-type instruction format

Fields

```
Opcode opcode §source
```
```
uint5 imm_4_0 §source
```
```
Funct3 funct3 §source
```
```
Reg rs1 §source
```
```
Reg rs2 §source
```
```
uint7 imm_11_5 §source
```

struct B_type §source

B-type instruction format

Fields

```
Opcode opcode §source
```
```
uint1 imm_11 §source
```
```
uint4 imm_4_1 §source
```
```
Funct3 funct3 §source
```
```
Reg rs1 §source
```
```
Reg rs2 §source
```
```
uint6 imm_10_5 §source
```
```
uint1 imm_12 §source
```

struct U_type §source

U-type instruction format

Fields

```
Opcode opcode §source
```
```
Reg rd §source
```
```
uint20 imm_31_12 §source
```

struct J_type §source

J-type instruction format

Fields

```
Opcode opcode §source
```
```
Reg rd §source
```
```
uint8 imm_19_12 §source
```
```
uint1 imm_11 §source
```
```
uint10 imm_10_1 §source
```
```
uint1 imm_20 §source
```

union Instr §source

Fields

enum Format : uint3 §source

Values

template <Base ISA>
inline Types<ISA>::Decoded decode_format(Instr instr, Format format) §source

Decode instruction word in given instruction format

Arguments

```
Instr instr
```
Instruction word
```
Format format
```
Instruction format

Index

processor.risc_v.isa ≡