processor.risc_v.internal.decoder ≡

Internal implementation of RISC-V decoder.

enum Option : uint3 §source

Values

  • HartsShareDMEM = 2 §source

    Data memory is implemented as internally instantiated tightly coupled memory, with size in bytes specified by DMEM_LENGTH template argument. By default each hart has its separate block of data memory with address space spanning [DMEM_ORIGIN, DMEM_LENGTH). In multi-hart configuration when harts have their own DMEM block the DMEM_LENGTH must be a power of 2. The Option::HartsShareDMEM flags can be specified in CONFIG template argument to enable shared data memory, e.g. to allow programs running on different harts to communicate via memory. With shared DMEM the DMEM_LENGTH does not need to be a power of 2.

  • NoExceptionForCompressedEncoding = 4 §source

    Disables checking of lower two bits of instruction word which are used for compressed instruction encoding. This allows saving FPGA block RAM by synthesizing out these bits.

enum ControlOp : uint1 §source

Values

enum Condition : uint2 §source

Values

struct ControlInstr §source

Fields

enum ComputeOp : uint3 §source

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enum LogicalOp : uint2 §source

Values

struct BaseInstr §source

Fields

enum MulIn : uint1 §source

Values

enum MulOut : uint1 §source

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struct MulInstr §source

Fields

union ComputeInstr §source

Fields

enum MemoryOp : uint1 §source

Values

enum MemorySize : uint2 §source

Size of memory load/store

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struct MemoryInstr §source

Fields

enum SystemOp : uint3 §source

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struct SystemInstr §source

Fields

enum InstrKind : uint2 §source

Values

struct Decoded §source

Fields

template <auto EXTENSIONS, auto CONFIG>
inline Decoded decode_instr(Instr instr, (RVG) -> Format custom_decode) §source