processor.risc_v.internal.decoder ≡
Internal implementation of RISC-V decoder.
enum Option : uint3 §
Values
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HartsShareDMEM = 2 §
Data memory is implemented as internally instantiated tightly coupled memory, with size in bytes specified by
DMEM_LENGTHtemplate argument. By default each hart has its separate block of data memory with address space spanning[DMEM_ORIGIN, DMEM_LENGTH). In multi-hart configuration when harts have their own DMEM block theDMEM_LENGTHmust be a power of 2. TheOption::HartsShareDMEMflags can be specified inCONFIGtemplate argument to enable shared data memory, e.g. to allow programs running on different harts to communicate via memory. With shared DMEM theDMEM_LENGTHdoes not need to be a power of 2. -
NoExceptionForCompressedEncoding = 4 §
Disables checking of lower two bits of instruction word which are used for compressed instruction encoding. This allows saving FPGA block RAM by synthesizing out these bits.
enum ControlOp : uint1 §
enum Condition : uint2 §
struct ControlInstr §
enum ComputeOp : uint3 §
enum LogicalOp : uint2 §
struct BaseInstr §
enum MulIn : uint1 §
enum MulOut : uint1 §
struct MulInstr §
union ComputeInstr §
enum MemoryOp : uint1 §
enum MemorySize : uint2 §
struct MemoryInstr §
Fields
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MemoryOp op §
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MemorySize size §
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bool sign_extend §
enum SystemOp : uint3 §
struct SystemInstr §
enum InstrKind : uint2 §
struct Decoded §
template <auto EXTENSIONS, auto CONFIG> inline Decoded decode_instr(Instr instr, (RVG) -> Format custom_decode) §