processor.risc_v.internal.core ≡

This is internal implementation of RISC-V processor core. Use definitions from processor.risc_v module instead.

enum Trap : uint3 §source

System trap/exception identifier

Values

  • InvalidInstructionAddress = 0 §source

    Program counter moved to address outside specified instruction memory address space.

  • AccessFault = 1 §source

    Memory access to address outside of data memory and memory mapped IO address spaces.

  • IllegalInstruction = 2 §source

    Invalid or illegal instruction was decoded.

  • ECALL = 4 §source

    ECALL instruction was executed.

  • EBREAK = 5 §source

    EBREAK instruction was executed.

enum Optimize : uint1 §source

Optimization configuration bits

Values

  • Area = 0 §source

    Optimize for minimal area.

  • Fmax = 1 §source

    Optimize for maximum frequency.

template <
    auto HARTS,
    auto IMEM_LENGTH,
    auto DMEM_LENGTH,
    auto MMIO_LENGTH = 0,
    auto IMEM_ORIGIN = 0,
    auto DMEM_ORIGIN = ((IMEM_ORIGIN + IMEM_LENGTH) << 2),
    auto MMIO_ORIGIN = (DMEM_ORIGIN + DMEM_LENGTH),
    auto IMEM_TCM_SIZE = IMEM_LENGTH,
    template <typename, auto> typename DataMemory = memory_norep,
    auto EXTENSIONS = Extension::None,
    auto CONFIG = Optimize::Area,
    Base ISA = Base::RV32I,
    auto BTB_SIZE = 1024,
    template <typename, auto> typename InstrMemory = memory_init
    >
class Core §source

Aliases

  • using imem_addr_t = index_t<IMEM_LENGTH> §source

    Address of 32-bit word in instruction memory.

  • using dmem_addr_t = index_t<DMEM_LENGTH> §source

    Address of byte in data memory.

  • using int_t = Types<ISA>::int_t §source

    Signed, XLEN bits wide integer.

  • using uint_t = Types<ISA>::uint_t §source

    Unsigned, XLEN bits wide integer.

  • using hart_index_t = index_t<HARTS> §source

    Index of hardware thread (hart).

  • using system_trap_t =
    ( Core::hart_index_t hid, Trap trap, Core::imem_addr_t addr
    ) -> optional<Core::imem_addr_t> §source

    Type of callback to handle system exceptions and traps.

    Arguments

  • using trace_t =
    ( Core::hart_index_t hid,
    Core::imem_addr_t addr,
    Core::uint_t inst,
    Decoded decoded,
    optional<Core::int_t> value
    ) -> void §source

    Type of dynamic instruction trace callback.

    Arguments

    • Core::hart_index_t hid

      Identifier of the hart executing the instruction.

    • Core::imem_addr_t addr

      Address of 32-bit instruction word.

    • Core::uint_t inst

      Instruction word.

    • Decoded decoded

      Decoded instruction.

    • optional<Core::int_t> value

      If valid specifies value written by instruction to destination register specified by decoded.format.rd.

  • using mmio_access_t =
    ( Core::hart_index_t hid,
    Core::uint_t load_addr,
    Core::uint_t store_addr,
    MemorySize size,
    bool sign_extend,
    optional<Core::int_t> value
    ) -> optional<Core::int_t> §source

    Type of callback to handle memory mapped IO access. If the access operation completes immediately, the is_valid of the returned result should be set to true. For load access the value of the returned result is the result of the load. For store access the value of the returned result is ignored. If the operation will complete asynchronously the is_valid of the returned result should be set to false, and execution environment should indicate completion of load/store by calling the mmio_load_result or mmio_store_completed method respectively.

    Arguments

    • Core::hart_index_t hid

      Identifier of the hart executing the load.

    • Core::uint_t load_addr

      Memory mapped IO address used for load MMIO access.

    • Core::uint_t store_addr

      Memory mapped IO address used for store MMIO access.

    • MemorySize size

      Size of MMIO access.

    • bool sign_extend

      Boolean flag specifying if sub-word load should be sign-extended.

    • optional<Core::int_t> value

      Value to be stored, valid for store MMIO access

  • using mmio_load_t =
    ( Core::hart_index_t hid,
    Core::uint_t addr,
    MemorySize size,
    bool sign_extend
    ) -> optional<Core::int_t> §source

    Type of callback to handle load from memory mapped IO. The load result may be returned immediately, by setting is_valid of the callback return value to true, or asynchronously, by calling mmio_load_result method after the callback returns.

    Arguments

    • Core::hart_index_t hid

      Identifier of the hart executing the load.

    • Core::uint_t addr

      Memory mapped IO address to load from.

    • MemorySize size

      Size of load.

    • bool sign_extend

      Boolean flag specifying if sub-word load should be sign-extended.

  • using mmio_store_t =
    ( Core::hart_index_t hid,
    Core::uint_t addr,
    MemorySize size,
    Core::int_t value
    ) -> bool §source

    Type of callback to handle store to memory mapped IO. The callback should return true if the program running on the core can consider the store as committed, or false if the store should be considered as pending. In the latter case, the hart that made the request is stalled until the execution environment indicates the store as completed by calling the mmio_store_completed method.

    Arguments

  • using external_fetch_t =
    ( Core::hart_index_t hid, Core::imem_addr_t addr
    ) -> optional<Core::uint_t> §source

    Type of external instruction fetch handler.

    Arguments

  • using custom_decode_t = (RVG major_opcode) -> Format §source

    Type of callback of custom instruction decode handler.

    Arguments

    • RVG major_opcode

      Major opcode of the instruction.

  • using custom_execute_t =
    ( Core::hart_index_t hid,
    RVG major_opcode,
    Funct3 minor_opcode,
    Core::int_t op1,
    Core::int_t op2,
    Core::int_t imm,
    Funct7 funct7
    ) -> Core::int_t §source

    Type of callback to execute custom instruction

    Arguments

    • Core::hart_index_t hid

      Identifier of the hart executing the instruction.

    • RVG major_opcode

      Major opcode of the instruction.

    • Funct3 minor_opcode

      Minor opcode of the instruction (undefined for instructions using format U or J).

    • Core::int_t op1

      First operand. Contains value of source register 1 (undefined for instructions using format U or J).

    • Core::int_t op2

      Second operand. Contains value of source register 2 for formats that specify it, or an immediate otherwise.

    • Core::int_t imm

      Immediate (undefined for instructions using R format)

    • Funct7 funct7

      funct7 field of decoded instructions using R format, undefined otherwise.

Methods